TM DSG SiNT MOSFET with a inner gate and outer gate are shown with

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Subband profile along the device length (left), and current

ION/IOFF ratio comparison of this work with reports in literature

Modelled and experimental Hall voltage response in vertical Hall

Effect of 3 nm gate length scaling in junctionless double

SS and DIBL comparison of this work with reports in literature

Effect of 3 nm gate length scaling in junctionless double

ID versus VDS curves of TM DSG SiNT MOSFET with

Modelled and experimental Hall voltage response in vertical Hall

Schematic of the real-space representation of an electron device

CGG vs VGS curve of Si for SiO2 + HfO2 as gate oxide with metal

Comparison between the current in a Ge quantum-well diode